1. Field of the invention
The present invention relates to a roll call circuit, and more specifically to a roll call reading circuit for a semiconductor memory having a plurality of redundant word lines or a plurality of redundant column lines.
2. Description of related art
Recent semiconductor memories are inclined to have a large storage capacity, and therefore, have an increased number of word lines and column lines. With this inclination, the recent semiconductor memories have redundant word lines and redundant column lines for lowering defective operation. Therefore, most of the semiconductor memories are provided with a roll call circuit for discriminating use or non-use of each redundant memory line (such as redundant word lines and redundant column lines) at the time of evaluating a product and of analyzing a defective product.
Referring to FIG. 1, there is shown a circuit diagram of one example of the conventional roll call circuit. The shown conventional roll call circuit includes a data-out buffer 12 for outputting data on an input/output pad I/O, a data amplifier 17 for amplifying data on a pair of complementary lines RWBST and RWBSN of an internal read/write bus so as to supply the amplified data to the data-out buffer 12, a sense amplifier data reading circuit 16 receiving a memory cell data from a sense amplifier (not shown in FIG. 1) to supply the received memory cell data to the pair of complementary lines RWBST and RWBSN, and a roll call result reading circuit 15 for supplying a roll call discrimination result to the pair of complementary lines RWBST and RWBSN.
Furthermore, the shown conventional roll call circuit includes a redundancy decoder 1 receiving internal address signals XADD.sub.1 to XADD.sub.9 which correspond to an X address supplied to external address input pins A.sub.1 to A.sub.9 (not shown), respectively. For example, if the X address supplied to the address input pin A.sub.1 is "1", the signal XADD.sub.1 is brought to a logical high level, or if the X address supplied to the address input pin A.sub.1 is "0" (zero), the signal XADD.sub.1 is brought to a logical low level. Similarly, the signals XADD.sub.2 to XADD.sub.9 are brought to the logical high level or the logical low level in accordance with the value of the X address supplied to the address input pins A.sub.2 to A.sub.9, respectively. This redundancy decoder 1 determines whether or not a redundancy word line should be selected.
The shown conventional roll call circuit also includes an X decoder 6 receiving the signals XADD.sub.1 to XADD.sub.9, an internal address signal XADD.sub.0 brought to the logical high level or the logical low level in accordance with the value of the X address supplied to an external address input pins A.sub.0 (not shown), and an output XRDS of the redundancy decoder 1. The X decoder 6 determines on the basis of its inputs XADD.sub.0, XADD.sub.1 to XADD.sub.9, which of words lines should be selected.
The shown conventional roll call circuit further includes a roll call decoder 14 receiving the output XRDS of the redundancy decoder 1, a one-shot precharge signal YRD generated by an ATE) generation circuit 9, and a signal RCLB. The one-shot precharge signal YRD generated by the ATD generation circuit 9 is used for precharging a dynamic circuit (not shown in FIG. 1 ) incorporated in the roll call decoder 14. At the time of a roll call testing, the roll call decoder 14 generates an output RCSB on the basis of the result of the roll call testing.
The sense amplifier data reading circuit 16 includes a pair of transfer gates composed of N-channel transistors Tr.sub.46 and Tr.sub.45, respectively, which are respectively connected between the pair of complementary lines RWBST and RWBSN and a pair of complementary data lines READT and READN from the sense amplifier, and a NOR gate NOR.sub.3 for outputting a control signal to a gate of each of the transfer gate transistors Tr.sub.45 and Tr.sub.46. The NOR gate NOR.sub.3 has one input connected to receive an input signal BSLB and the other input connected to receive an output RCE of the roll call result reading circuit 15.
The roll call result reading circuit 15 includes a NOR gate NOR.sub.2 having one input connected to an output RCSB of the roll call decoder 14 and the other input connected to receive the signal RCLB, a transfer gate N-channel transistor Tr.sub.43 connected between the line RWBSN and ground and having a gate connected to an output of the NOR gate NOR.sub.2, and another transfer gate N-channel transistor Tr.sub.44 connected between a voltage supply line and the line RWBST and having a gate connected to the output of the NOR gate NOR.sub.2.
The pair of complementary lines RWBST and RWBSN are clamped to a voltage supply voltage by means of a clamp circuit 13 formed of a pair of a gate-grounded P-channel transistors Tr.sub.9 and Tr.sub.10 connected between the voltage supply line and the pair of complementary lines RWBST and RWBSN, respectively.
Now, operation will be described.
First, an operation for reading a memory cell data is as follows: The signal RCLB is a test mode activation signal which is brought to the logical low level only when the roll call test is carried out. Therefore, at the time of reading the memory cell data, since signal RCLB is at the logical high level, the signal. RCE is at the logical low level. Accordingly, during a low period of the input signal BSLB, the N-channel transistors Tr.sub.45 and Tr.sub.46 are ON, so that the sense amplifier data READT and READN are transferred to the lines RWBST and RWBSN, respectively, and therefore, amplified by the data amplifier 17 so as to outputted through the data-out buffer 12 to the input/output pad I/O. In this condition, since the signal RCE is at the logical low level, the N-channel transistors Tr.sub.43 and Tr.sub.44 are OFF, and therefore, no data is sent from the roll call result reading circuit 15 to the lines RWBST and RWBSN.
The following is operation of the roll call testing.
At the time of the roll call testing, the signal RCLB is brought to the logical low level. Therefore, the data on the lines RWBST and RWBSN is determined by the level of the output signal RCSB of the roll call result reading circuit 14. If the output signal RCSB is at the logical low level, the signal RCE is brought to the logical high level, so that the N-channel transistors Tr.sub.43 and Tr.sub.44 are ON and the N-channel transistors Tr.sub.45 and Tr.sub.46 are OFF. Accordingly, the line RWBST is brought to the 25 logical high level, and the line RWBSN is brought to the logical low level. This data is amplified by the data amplifier 17 and outputted through the data-out buffer 12 to the input/output pad I/O.
If the output signal RCSB is at the logical high level, the N-channel transistors Tr.sub.43 and Tr.sub.44 are OFF and the N-channel transistors Tr.sub.45 and Tr.sub.46 are rendered ON during the logical low level period of the input signal BSLB. Accordingly, the sense amplifier data is transferred to the lines RWBST and RWBSN, and amplified by the data amplifier 17 so as to outputted through the data-out buffer 12 to the input/output pad I/O.
As mentioned above, at the time of a roll call testing, the roll call decoder 14 generates an output RCSB on the basis of the result of the roll call testing. Therefore, if the memory cell is previously written to the effect that the sense amplifier data READT is at the logical high level and the sense amplifier data READN is at the logical low level, the data outputted on the input/output pad I/O changes dependently upon whether the signal RCSB is at the logical high level or at the logical low level.
Thus, if the roll call testing is carried out while changing the combination of the high level and the low level in the signals XADD.sub.1 to XADD.sub.9, it is possible to discriminate, from the signal appearing on the input/output terminal I/O, use or non-use of the redundancy word line in accordance with the condition of XADD.sub.1 to XADD.sub.9.
Referring to FIG. 2, there is shown a circuit of the roll call decoder 14 included in the conventional roll call circuit shown in FIG. 1. The shown roll call decoder 14 includes an inverter INV.sub.14 receiving the one-shot precharge signal YRD, a P-channel transistor Tr.sub.48 having a gate connected to an output of the inverter INV 14, and another P-channel transistor Tr.sub.47 having a gate connected to receive the input signal RCLB. These transistors Tr.sub.47 and Tr.sub.48 are connected in series between the voltage supply line and a precharge node "N". The input signal RCLB is also applied to a gate of an N-channel transistor Tr.sub.49, which is connected between the precharge node "N" and ground. Another N-channel transistor Tr.sub.50, which has a gate connected to receive the output signal XRDS, is also connected between the precharge node "N" and ground. The precharge node "N" is connected to a cascaded inverters INV.sub.15 and INV.sub.16, which operate to buffer a level on the precharge node "N" so as to generate the output RCSB.
Now, operation of the roll call decoder 14 will be described.
At the time of the roll call testing, since the input RCLB is the logical low level, the precharge node "N" is precharged to the voltage supply Voltage level during the logical high level period of the one-shot precharge signal YRD. If tile input signal XRDS is at the high level, a level on the precharge node "N" is determined by a resistance division ratio of the transistors Tr.sub.47, Tr.sub.48 and Tr.sub.50. The inverter INV.sub.15 is set or configured to have such a threshold that the inverter INV.sub.16 outputs a logical high level as the output RSCB at this time.
At a time other than the roll call testing, the input RCLB is at the logical high level, and therefore, the transistor Tr.sub.49 is ON so that the precharge node "N" is fixed to a ground level.
Here, if the redundancy word line is used, the XRDS is at the logical high level, and if the redundancy word line is not used, the XRDS is at the logical low level. Therefore, the roll call can be realized.
In the above mentioned roll call circuit, since the sense amplifier data is read out when the roll call decoder output RCSB is at the logical high level, if there is a failure in the sense amplifier, the memory cell and a write circuit, there is possibility that the data outputted onto the input/output pad is inverted.
Furthermore, since one roll call decoder and one roll call result reading circuit are required for each one redundancy word line, in the case that a plurality of redundancy word lines are provided, a required circuit area and the required number of signal lines are increased. To an extreme, there is possibility that the output line pairs RWBST and RWBSN, the data amplifiers, the data-out buffers and the input/output buffers become shorted.